This invention relates to a semiconductor device in which MOS elements are integrated.
Various MOS devices are widely used nowadays. FIG. 1 is a plan view showing a prior art MOS gate array. It can be seen that a gate array portion 12 is provided in the central portion of a chip 10. Also, a large number of input/output cells 14 are arranged along the periphery of the chip 10. The input/output cell 14 consists of a p-channel MOS region 16, a bonding pad 18 and an n-channel MOS region 20. It should be noted that a parasitic PNP transistor is formed in the region between the p-channel MOS region 16 and the n-channel MOS region 20, with the result that a latch-up phenomenon is caused between the regions 16 and 20. In order to prevent the difficulty, it is necessary to decrease the current amplification factor of the parasitic transistor by disposing the regions 16 and 20 sufficiently apart from each other. However, it is unavoidable to decrease the number of input/output cells 14 arranged along the periphery of the chip 10. If the number of cells is decreased, the number of bonding pads is also decreased, rendering it difficult to select the bonding pad to which a lead wire is to be connected. Thus, unsatisfactory bonding is likely to be caused. Further, the adjacent input/output cells 14 are opposite to each other in the arrangement of the p-channel MOS region 16 and the n-channel MOS region 20 so as to prevent the latch-up phenomenon between the adjacent cells. As a result, the bonding pads 18 are rendered nonuniformly apart from each other. Also, the input/output terminals of the regions 16 and 20 with respect to the gate array portion 12 are rendered nonuniformly apart from each other. Thus, the bonding operation and the wiring in the final step are rendered difficult.